a) Field of the Invention
The present invention relates to a semiconductor device and more particularly to a structure of a semiconductor device with highly integrated DRAMs and its manufacture method.
b) Description of the Related Art
In large scale integrated (LSI) circuits having mostly logic circuits fabricated by process techniques of 0.5 .mu.m rule, mainly static random access memories (SRAM) are presently used as built-in memories because of its light process load. Since a memory cell of SRAM is formed only by transistors, the memory manufacture processes can be shared with logic manufacture processes.
FIG. 4A shows a general circuit structure of an SRAM. As shown, one memory cell of SRAM requires transistors T1 to T4 constituting a flip-flop and read/write transistors T5 and T6 connected to data/word lines, totalling six transistors.
Since one memory cell of SRAM requires six transistors, it is said a realizable minimum cell size is 50 to 60 .mu.m.sup.2 even with an ingenious layout pattern. Under a growing trend towards higher integration satisfying demands for large capacity of memories and small size of chips, use of SRAMs does not realize a sufficient integration degree.
In such circumstances, DRAMs simpler in structure than SRAMs are being used in a built-in memory having a capacity of 1 Mbit or larger.
FIG. 4B shows a general circuit structure of a DRAM. One memory cell of DRAM is constituted by one transistor Td and one capacitor Cd. One current terminal of the transistor is connected to the data line, and the other current terminal is connected via the capacitor Cd to the plate line. The gate terminal of the transistor Td is connected to the word line. Read/write of one bit is carried out by charging/discharging the capacitor Cd via the transistor Td. As compared to SRAMs, high integration of DRAMs is possible because of a less number of constituent elements of one memory cell.
Even with DRAMs, however, the structure of a cell capable of further reducing the cell size and realizing higher integration has been desired for a built-in memory having a capacity of 4 Mbit or larger.
Presently, for DRAMs having a memory size of 4 Mbit or larger, a cell structure called a stacked capacitor (STC) type is used dominantly. For DRAMs having a memory size of about 1 Mbit, a cell structure called a planar type is used.
FIG. 5A shows an example of a cell structure of a currently used STC type DRAM. A semiconductor substrate 51 has a field oxide film 52 defining an active region. The active region has a transistor formed therein, the transistor being constituted by source/drain regions made of diffusion layers 53a and 53b (hereinafter the diffusion layer 53a is called a source region and the diffusion layer 53b is called a drain region) and a gate electrode 54a made of a first level polysilicon layer.
A portion encircled by a broken line .alpha. in FIG. 5A corresponds to the capacitor. A second level polysilicon film 55 and a third level polysilicon film correspond, respectively, to the lower and upper electrodes of the capacitor. A thin silicon nitride film C1 interposed between the lower and upper electrodes corresponds to the capacitor dielectric layer. This capacitor is formed above the drain region 53b, with the lower electrode 55 being electrically connected to this drain region 53b.
The transistor and capacitor are covered with an interlayer insulating film 57. An interconnection 58 is led from the source region 53a via the contact hole.
This STC type DRAM cell has such a structure that the capacitor is stacked on the transistor. The transistor is therefore required to be formed before the capacitor is formed. A problem therefore arises that capacitor forming processes with heat may degrade the performance of the transistor already formed. In addition, because of its complicated structure, the number of necessary processes is large.
FIG. 5B shows an example of a cell structure of a currently used planar type DRAM. A semiconductor substrate 51 has a field oxide film 52 defining an active region. The active region has a transistor formed therein, the transistor being constituted by a source region 53a, a drain region 53b, and a gate electrode 54a formed on a thin gate oxide film on the substrate surface.
A portion encircled by a broken line .beta. in FIG. 5B corresponds to the capacitor. A shallow impurity diffusion layer 53c is formed in the substrate surface layer continuously with the drain region 53b. On the surface of the impurity diffusion layer 53c, an SiO.sub.2 film C2 is formed, on which a first level polysilicon film 54b is formed. The diffusion layer 53c corresponds to the lower electrode of the capacitor, the first level polysilicon film 54b corresponds to the upper electrode, and the SiO.sub.2 film C2 corresponds to the dielectric layer. The transistor and capacitor are covered with an interlayer insulating film 57. An interconnection 58 is led from the source region 53a via the contact hole.
In this planar type DRAM cell, it is necessary to form, in addition to the source/drain regions of the transistor, the impurity diffusion layer as the lower capacitor electrode in the substrate surface layer. In this planar type DRAM cell, the capacitor dielectric layer is made of an SiO.sub.2 film formed at the same time when the gate insulating film is formed. Since an SiO.sub.2 film has a relatively small dielectric constant, a required area of the capacitor is broad in order to retain a necessary capacitance. Because of these reasons, there is a limit in reducing the cell size of a planar type DRAM.
As shown in FIG. 5B, an interconnection 55 made of a second level polysilicon film is being formed in the interlayer insulating film 57 above the capacitor. This interconnection 55 is essential for interconnection to the gate electrode of an adjacent memory cell, and is formed above the capacitor to reduce the cell size. An electrostatic capacitance is therefore generated between the upper capacitor electrode 54b and the interconnection 55. In order to escape the influence of this capacitance, the interlayer insulating film between the interconnection 55 and upper electrode 54b should be made thick.
As above, if SRAM is used as a built-in memory of LSI, the cell size becomes large and high integration is difficult. If STC type DRAM is used as a built-in memory, the manufacture processes become complicated and heat treatments after the formation of MOSFET may degrade the performance of transistors. If planar type DRAM is used, there is a limit in reducing the cell size although the manufacture processes are relatively simple.